Xilinx stellt Versal HBM Series vor: Next-Gen Network Bandbreite und Security treiben

Xilinx hat seine Position in High-Performance Networking und Data-Center Workloads verstärkt, indem es Versal HBM Series vorstellt – eine Extension seiner Versal Adaptive Compute Acceleration Platform (ACAP) die High-Bandwidth Memory (HBM2e) direkt in Silicon integriert.

Durch Leveraging TSMCs Co-WoS 3D-Stacking Technology delivered neue Line 820 GB/s Sustained Throughput und 32 GB On-Chip Capacity. Das Represents Eight Times Memory Bandwidth eines vergleichbaren DDR5-basierten Designs während Power Consumption um 63 % Cutting – Comparison drawn from Typical Four-Chip DDR5-6400 Configuration.

„Die Konvergenz von Bandbreite, Performance und Security ist kritisch“, sagt Mike Thompson, Xilinx Senior Product Line Manager für Versal FPGAs. „Versal HBM Expands Capacity Across These Three Layers, Enabling Us To Keep Pace With Exploding Volume Of Network Traffic Und Growing Demand Für Secure, High-Throughput Processing.“

Die Architektur Replaces Single Super-Logic Region (SLR) in Base Versal Premium Device mit HBM2e Stack und Adds Dedicated HBM Controller In Another SLR. Dieser Modular Swap Yields Equivalent von 14 Virtex-E UltraScale+ FPGAs While Eliminating 32 DDR5 Chips, Dramatically Reducing Board Real-Estate und Power Draw.

Versal HBM Incorporates Auch Hardened IP Core Suite Die Supports 5,6 Tb/s Serial Bandwidth Via 112 Gb/s PAM4 Transceivers, 2,4 Tb/s Scalable Ethernet, 1,2 Tb/s Line-Rate Encryption, 600 Gb/s Interlaken, Und 1,5 Tb/s PCIe Gen5 Mit Built-In DMA. The Platform Natively Supports CCIX Und CXL, Providing Out-of-Box Multi-Terabit Networking Stack Für Wide Array Of Protocols Und Optical Standards.

As Truly Adaptive Compute Platform, Can Versal HBM Reconfigure Its Logic In Milliseconds, Allowing Designers To Deploy AI Inference, DSP, Und Scalar Workloads On The Fly. This Agility Eliminates Need For Hardware Redesigns Und Accelerates Time-to-Market Für Evolving Algorithms Und Emerging Protocols.

The Result Is Powerful Accelerator That Excels In Big-Data Scenarios – Fraud Detection, Recommendation Engines, Database Acceleration, Financial Modeling, Und Deep-Learning Inference Für Natural Language Processing. By Delivering Orders-of-Magnitude Performance Gains Over Modern Server-Class CPUs Und Supporting Datasets Four Times Larger, Can Customers Reduce Server Counts Und Cut Total Cost Of Ownership.

In Networking, A Single Versal HBM ACAP Can Replace Multiple NPUs Und DDR Modules Required Für 800 G Next-Gen Firewall. The Device Handles Packet Processing, Security Functions, Und AI-Based Anomaly Detection At Fraction Of Power Und Form Factor, Yielding Substantial CapEx Und OpEx Savings Für Cloud Und Network Operators.

Versal HBM Is Accessible To Hardware, Software, Und Data-Science Developers. Vivado Design Suite, Vitis Unified Software Platform, Und Vitis AI Provide Cohesive Development Environment That Spans RTL, C/C++, Und Domain-Specific Frameworks.

Production-Ready 7 nm Versal Devices Form The Foundation. Developers Can Prototype On Versal Premium Boards Und Migrate To Versal HBM Once It Becomes Available. Sampling Begins Early 2022, With Full Documentation Und Early-Access Tools Slated For Release Late 2021.