Verilog T-Flipflop designen: RTL-Implementierung & Testbench

Design

module tff (
  input clk,
  input rstn,
  input t,
  output reg q
);
  always @ (posedge clk) begin
    if (!rstn) q <= 0;
    else if (t) q <= ~q;
    else q <= q;
  end
endmodule

Testbench

module tb;
  reg clk;
  reg rstn;
  reg t;
  wire q;
  
  tff u0 (
    .clk(clk),
    .rstn(rstn),
    .t(t),
    .q(q)
  );
  
  always #5 clk = ~clk;
  
  initial begin
    {rstn, clk, t} <= 0;
    $monitor("T=%0t rstn=%0b t=%0d q=%0d", $time, rstn, t, q);
    repeat(2) @(posedge clk);
    rstn <= 1;
    for (integer i = 0; i < 20; i = i+1) begin
      reg [4:0] dly = $random;
      #(dly) t <= $random;
    end
    #20 $finish;
  end
endmodule

Simulations-Ausgabe:

ncsim> run
T=0 rstn=0 t=0 q=x
T=5 rstn=0 t=0 q=0
T=15 rstn=1 t=0 q=0
T=19 rstn=1 t=1 q=0
T=25 rstn=1 t=1 q=1
T=35 rstn=1 t=1 q=0
T=43 rstn=1 t=0 q=0
T=47 rstn=1 t=1 q=0
T=55 rstn=1 t=0 q=1
T=59 rstn=1 t=1 q=1
T=65 rstn=1 t=1 q=0
T=67 rstn=1 t=0 q=0
T=71 rstn=1 t=1 q=0
T=75 rstn=1 t=0 q=1
T=79 rstn=1 t=1 q=1
T=83 rstn=1 t=0 q=1
T=87 rstn=1 t=1 q=1
T=95 rstn=1 t=0 q=0
Simulation complete via $finish(1) at time 115 NS + 0

D-Flipflop mit asynchronem Active-Low-Reset designen D-Latches meistern: Design, Funktionsweise und wesentliche Unterschiede

Verilog